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PCIe Gen5/4 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. An important capability of a Physical Layer protocol aware Retimer is to execute the Phase 2/3 of the equalization procedure in each direction. A maximum of two Retimers are permitted between an Upstream and a Downstream Port.
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Block Diagram of the PCIe Gen5/4 Retimer IP Core
Retimer IP
- USB3.x Gen2 Retimer Controller
- USB3.2 Gen2 Single Lane Re-Timer IP Core
- USB Type-C 40 Gb/s Multi-Protocol Switch and Bi-Directional Bit-Level Retimer
- PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 4.0 Controller with AMBA AXI interface
- USB 3.x Device IP