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32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
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PCIe Gen5 Switch (FPGA)
Mobiveil’s PCIe Gen5 Switch utilizes FPGA PCIe Hard IP stacks configured as switch upstream/downstream, integrated with our Switch Fabric to deliver a versatile PCIe Switch Solution. Ideal for desktop, server, mobile, networking, and telecom applications, our design optimizes link utilization, latency, reliability, power consumption, and silicon footprint. Its configurable, layered architecture supports various application logics, PHY designs, and technologies, ensuring easy migration across FPGA platforms (AMD/Intel).
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Block Diagram of the PCIe Gen5 Switch (FPGA) IP Core
PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP