The PCI Express Specification allows Endpoints that incorporate more than one physical PCIe-Function. Such Endpoints are called Multi-Function Devices. The big advantage of a Multi-Function Device is, that a separate device driver can be associated to each physical Function. This simplifies driver development and maintenance significantly by separating different peripheral Functions logically into different device drivers.
The Xilinx PCIe Hardblocks in the 7 Series device family however do not support more than one physical PCIe Function and do not support Multi-Function Devices natively.
Smartlogic’s new patented Multi-Function Extension IP-Core removes this restriction by extending the Xilinx PCIe Hardblock with up to 6 physical PCIe Functions. Compared to a PCIe Soft IP-Core solution with Multi-Function support, the Smartlogic IP-Core uses only a fraction of logic resources and will fit even in the smallest Artix FPGA Devices.
- Extends the Xilinx integrated PCI-Sig compliant PCIe Hardblock by up to 6 true physical PCI Express Functions (not virtual Functions requiring SRIOV capability)
- Each BAR of each Function is mapped to an memory mapped AXI4 Master
- The user defines, if all PCIe-Functions communicate with either the same or with a different device driver
- 32 and 64-Bit BAR support for all Functions
- BARs can be defined independently at compile time.
- Each Function can issue interrupts (MSI only)
- Detection of Signal Integrity problems on PCIe Link (for productional testing)
- Device Driver Package available as option
- Link Speeds Gen 1 or 2, Link Width x1
- Available for A7, K7 and Zynq-7000 (ask for the availability for other FPGA Families)
Block Diagram of the PCIe Multifunction Extension IP Core for Xilinx FPGAs