iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface.
- Compliant with SD Host Controller Standard Specification Version 2.0
- Compliant with SD Physical Layer Specification Version 2.0
- Compliant with eMMC Specification Version 4.41
- Supports 1-bit,4-bit SD/eMMC modes and 8-bit eMMC modes.
- Supports SD Card Detection input pin
- Supports SD Card Write Protection input pin
- Supports programmable clock frequency generation to the SD/eMMC card.
- Supports Interrupt and ADMA2 transfer mode of operation.
- Individual 2Kbyte data buffer for read and write.
- Cyclic Redundancy Check (CRC) for command and data.
- Supports timeout monitoring for response, data, CRC token & busy.
- Supports a maximum block length of 2K-byte.
- Supports both single block and multi block data transfer.
- Supports power ON/OFF control to SD/eMMC card.
- Supports Gen1 x1 PCIe link for host processor interface
- Compatible with different FPGA Vendors PCIe Hard IP
- Configurable and ease of use in industrial and embedded applications
- Embedded and industrial applications development
- Consumer and Server applications
Block Diagram of the PCIe to SD/MMC Bridge IP Core