PCIe2.0 PHY & Controller
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
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PCIe2.0 IP
- PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
- PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
- PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
- PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process
- Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process