The Mentor Graphics PCMCIA core provides PCMCIA card 2.1 compliance to SoC devices. The core is capable of responding to cycles for attribute memory,common memory, and I/O modes up to the maximum rate allowed by the PCMCIAstandard. The core is designed to interface to the processor through the CoreFrame?or AHB interface. Direct memory access (DMA) is provided through a FIFO-like interface to an external DMA channel. The CoreFrame bus is a nonpipelined interface incorporating address, data, read strobe, write strobe, and a wait signal. The DMA channel interface is a non-pipelined interface that includes FIFO status, data, and read and write strobes. Interrupt status and masking registers allow polled or interrupt-driven firmware to service interrupt events.