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Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on FPGA and ASIC technologies.
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Block Diagram of the Peripheral Direct Memory Access Controller IP Core
DMA IP
- Northwest Logic AXI DMA Back-End Core from Rambus
- PCIe 5.0, 4.0, 3.1/3.0 Root Port, Endpoint, Dual-mode, Controller IP Core with Built-in Many-Channel DMA (vDMA), Legacy DMA, and Configurable AMBA AXI Interconnect
- Configurable PCI Express 2.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Configurable PCI Express 1.1 Supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Northwest Logic DMA Back-End Core from Rambus
- Windows & Linux Drivers for the Expresso DMA Core from Rambus