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PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
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Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on FPGA and ASIC technologies.
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Block Diagram of the Peripheral Direct Memory Access Controller IP Core
DMA IP
- Rambus AXI DMA Back-End Core
- Rambus PCIe 5.0 Controller with AMBA AXI interface
- Rambus PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Rambus PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Rambus DMA Back-End Core
- Rambus High-performance PCIe-AXI Bridge and/or scatter-gather DMA