English
You are here:
Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on FPGA and ASIC technologies.
Features
- AMBA AXI4-Lite slave bus
- AMBA AXI4 master bus
- Configurable number of peripheral channels
- 8, 16, 32 bits data transfer modes
- Upstream and downstream data aggregation to 32 bit chunks
- Various address modes
- Various arbiter priority schemes
- Circular buffer support
- Configurable independent upstream and downstream FIFOs
- Maskable interrupts
- Dedicated upstream and downstream peripherals DMA interface
- Fully synthesizable synchronous design with positive edge clocking
- DFT ready
Benefits
- Synthesizable RTL Verilog source code
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Silicon and FPGA proven
- Easy SoC integration
- Full implementation and maintenance support with individual approach
- Flexible licensing scheme
Deliverables
- Verilog RTL source code
- Verification suite
- Datasheet and integration guide
- C-header file
- Constraints
- Technical support
Block Diagram of the Peripheral Direct Memory Access Controller IP Core
View Peripheral Direct Memory Access Controller full description to...
- see the entire Peripheral Direct Memory Access Controller datasheet
- get in contact with Peripheral Direct Memory Access Controller Supplier
DMA
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- Many-Channel Centralized DMA Controller with AMBA AXI Interconnect
- Multi Channel DMA Flex IP Core for PCI-Express
- PCIe Endpoint with multiple industry standard AXI Interfaces
- CAN 2.0 Controller with DMA