The device consists of phase frequency detector (PFD), charge pump and lock detector (LD).
PFD compares phases of a divided VCO signal and a divided reference oscillator signal. PFD feeds control signal to charge pump at signals mismatch. Charge pump output current forms VCO control voltage.
Lock detector forms output logical “1” at input signals phase coincidence.
The block is fabricated on SMIC CMOS 0.18 um technology.
- SMIC CMOS 0.18 um
- Charge pump current control (40 uA, 60 uA, 80 uA, 100 uA)
- Wide range of charge pump output voltage (0.3 V…1.56 V)
- PFD polarity selection
- Lock time selection (64, 128, 216, 512 periods of reference frequency signal)
- Without external components
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Frequency synthesizer
- Functional signal generator
- Communication devices