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Phase Locked Loop (PLL) Macro
The PLL consist of the PLL loop, lock detect circuit and 9 output counters. The delta sigma modulator
& spread-spectrum clock generation logic is placed in the core (PLL wrapper) and can be removed if
fractional division is not needed.
& spread-spectrum clock generation logic is placed in the core (PLL wrapper) and can be removed if
fractional division is not needed.
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PLL IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC CLN7FF 7nm Spread Spectrum PLL - 700MHz-3500MHz
- Fractional-N Frequency Synthesizer PLL (3nm - 180nm)
- Ultra Low Area Frequency Synthesizer PLL (5nm - 90nm)
- 32kHz Ultra-Fast-Lock IoT PLL
- Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)