The Phase Locked Loop primitive in Virtex-5 FXT parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. The Phase Locked Loop (PLL) module is a wrapper around the PLL_ADV primitive that allows the PLL to be used in the EDK tool suite.
- Wrapper around the PLL_ADV primitive
- Full support for use with EDK 9.1 and later versions
- Configurable BUFG insertion
- Configurable output delay adjustment for PPC block clock insertion delay compensation
- Six output clocks with independently selectable frequencies