PHY IP for DisplayPort/Embedded DisplayPort TX

Features

• DisplayPort and Embedded DisplayPort v1.4
• Support RBR, HBR, HBR2, HBR3 rates for DisplayPort and UI_Rate_1 through UI_Rate_8 for Embedded DisplayPort
• Support wide range of reference clock rates
• Support both internal and external clock sources
• Automatic calibration of on-chip termination resistors
• Flexible x1/x2/x4 configuration support single/dual links in one macro
• AUX/HPD function available in separate macro
• SCAN, BIST, and loopback functions

Benefits

• Optimum SoC configurability
• Optimized PPA for mobile and consumer applications
• Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging

Deliverables

• Standard integration views: LEF abstract, timing views (.LIB), behavioral model (Verily), gate-level netlists (plural, SDF, DRC, LVS), ANT reports, and GDSII layout and layer map
• Synthesizable soft layer (primarily isolation logic) with SDC
• Complete documentation including user guide, integration guide, and programmer guide
• High Volume Manufacturing (HVM) kit
• Testboards available upon request

Applications

• Video
• Semiconductors
• Consumer Audio and Video

Block Diagram of the PHY IP for DisplayPort/Embedded DisplayPort TX

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