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PHY IP for DisplayPort/Embedded DisplayPort TX
The Cadence® PHY IP for DisplayPort/Embedded DisplayPort TX provides a configurable PHY IP that simplifies the design process without compromising performance, power, or silicon die area. The PHY IP is a lower-active and low-leakage power design crafted for mobile, wireless IoT, and consumer designs.
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Block Diagram of the PHY IP for DisplayPort/Embedded DisplayPort TX
DisplayPort IP
- USB 3.1/DisplayPort 1.4 IP Subsystem Solution
- DisplayPort 1.4a IP Core
- ASIL-B Ready ISO 26262 Certified VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- DisplayPort 1.4a Transmitter Link Controller
- DisplayPort 1.4a Receiver Link Controller
- Content Protection (HDCP) 2.2/2.3 embedded security modules (ESMs) for HDMI, DisplayPort, and USB 3.x Type-C interfaces