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PHY IP for HBM2 for Samsung 10LPP
Artificial intelligence (AI), high-performance computing (HPC), image processing, and autonomous driving applications generate and consume large volumes of data and require very high memory bandwidth. The Cadence® Denali® PHY IP for HBM2 for the Samsung 10LPP Process is an ideal solution for meeting these high-performance applications.
The PHY IP for HBM2 is comprised of architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. The PHY IP for HBM2 was developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Denali Controller IP for HBM2 as part of a complete memory subsystem solution.
The PHY IP for HBM2 is comprised of architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. The PHY IP for HBM2 was developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Denali Controller IP for HBM2 as part of a complete memory subsystem solution.
Features
- Lowest latency for data-intensive applications
- Memory controller interface uses DFI 4.0-like standard
- Advanced clocking architecture minimizes clock jitter
- DFI PHY Independent Mode for initialization and training
- Highest data rates with high-resolution delay adjust
- IEEE 1500 interface, BIST module, and loop-back function
- Designed for optimized interposer routing
- Debug and bring-up software
Benefits
- Derived from Cadence’s silicon-proven DDR and LPDDR IP designs
- Achieves highest data rates with detailed system guidelines
- Delivers maximum system margin with advanced clocking and I/O architectures
Deliverables
- GDS II macros with abstract in LEF
- Verilog post-layout netlist
- STA scripts for use at chip or standalone PHY levels
- Liberty timing model
- SDF for back-annotated timing verification
- Verilog models of I/O pads, and RTL for all PHY modules
- Verilog testbench with memory model, configuration files, and sample tests
- Documentation—integration and user guide, release notes
- Verification IP (VIP) set-up files
- Reference design for PCB and package
Block Diagram of the PHY IP for HBM2 for Samsung 10LPP
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