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PHY IP for PCIe 3.0 TSMC 28HPM
The PHY IP for PCIe 3.0 is designed according to PCIe 3.0 specification. Implemented on the TSMC 28HPM process, the PHY IP provides a cost-effective, low-power solution. The PHY IP for PCIe 3.0 operates at 8.0GTps, 5.0GTps, and 2.5GTps. The Physical Coding Sublayer (PCS) complies with the PIPE 3.0 (v0.9) and PIPE 4.2 specification, and provides support for the dynamic equalization features of PCIe 3.0. Flexibility in board design assured due to Cadence design-in kits. The PHY IP seamlessly connects to a Cadence, or third party, PIPE 3.0-compliant or PIPE 4.2-compliant controller. The PHY IP is dedicated to applications demanding low latency and high data transfer rates.
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PCIe 3 IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- PCIe 5.0 Controller IP supporting Root Complex, End Point, Switch Port compliant with PCIe 5.0/4.0/3.0/2.0/1.0 and fully synthesizable
- 1.25G-12.5G SerDes IP, Supports (PCIe Gen1/2, USB 3.0, SATA Gen 1/2/3) (Silicon Proven in SMIC 40LL)
- 1.25G-12.5G SerDes IP, Supports (PCIe Gen1/2/3, USB 3.0, SATA Gen 1/2/3) (Silicon Proven in TSMC 28HPC+)
- PHY IP for PCIe 3.0 TSMC 28HPC