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PHY IP for PCIe 3.0 TSMC 28HPM
The PHY IP for PCIe 3.0 is designed according to PCIe 3.0 specification. Implemented on the TSMC 28HPM process, the PHY IP provides a cost-effective, low-power solution. The PHY IP for PCIe 3.0 operates at 8.0GTps, 5.0GTps, and 2.5GTps. The Physical Coding Sublayer (PCS) complies with the PIPE 3.0 (v0.9) and PIPE 4.2 specification, and provides support for the dynamic equalization features of PCIe 3.0. Flexibility in board design assured due to Cadence design-in kits. The PHY IP seamlessly connects to a Cadence, or third party, PIPE 3.0-compliant or PIPE 4.2-compliant controller. The PHY IP is dedicated to applications demanding low latency and high data transfer rates.
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PCIe 3 IP
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- PCIe 4.0 SerDes PHY
- PCIe 3/2/1 SerDes PHY
- Configurable controllers for PCIe 3.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- PCIe 5.0, 4.0, 3.1/3.0 Root Port, Endpoint, Dual-mode, Controller IP Core with Built-in Many-Channel DMA (vDMA), Legacy DMA, and Configurable AMBA AXI Interconnect
- PCI Express (PCIe) Gen4 x4