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PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
XpressPCS for PCIe 5.0 is a logic design IP core implementing the Physical Coding Sublayer part of the PCIe 5.0 Specification. XpressPCS exposes a PIPE compliant user interface allowing connection to any PIPE 5.2 and PIPE 4.4.1 compliant PCIe PHY/MAC. It also exposes a transmit and receive interface to the PHY/PMA electrical sub-block along with messaging interface for Equalization and Lane Margining functionality. The comprehensive PHY/PMA interface is the result of years working with PCIe SerDes developers and guarantees XpressPCS IP can be used with any SerDes PMA implementation. XpressPCS is the ideal solution for PHY IP vendors and technology companies developing their own SerDes PHY looking to complement their SerDes PMA implementations with a full-featured silicon proven PIPE-compliant interface.
Features
- Compliant to the PIPE 5.2 Specification with Low Pin Count interface
- Compliant to the PIPE 4.4.1 Specification
- Statically selectable PIPE 5.2 or PIPE 4.4.1 interface
- Supports multi-lane SerDes PMA designs by instantiating multiple XpressPCS
- Supports PIPE interface width of 8-, 16-, 32-, and 64-bit (optional 128-bit)
- Supports PIPE interface clock from 62.5Mhz to 2Ghz
- Provides Low Power state control interface
- Messaging bus for Equalization and Lane Margining initialization
- Tx/Rx PMA interface with sideband signaling
- Fixed PMA data symbol width
Benefits
- XpressPCS is used by companies who don't have the expertise, the time, or the resources to develop, verify, and validate a complete PCS digital block for their PMA implementation:
- PCIe PHY IP providers, who are experts in analog design but lack the expertise in digital design, and looking for a proven PCS IP to complement their SerDes PMA offering
- Technology companies developing their own SerDes PMA, who may have digital design expertise but may be lacking the time or resources, and looking to sourcing a proven PCS IP to improve their time-to-market
Deliverables
- IP Verilog RTL source code
- Simulation environment
- Testbench
- PHY testsuite
- Synthesis scripts (Synopsys DC)
- Documentation
- XpressPCS reference manual
- PHY testsuite reference manual
Block Diagram of the PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
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PCIe IP
- PCIe 5.0 PHY in TSMC (16nm)
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Customizable Embedded Multi-port PCIe Switch
- PCIe 5.0 Controller
- XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support
- PCIE Gen5 digital controller