Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
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Block Diagram of the PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications

PCIe IP
- PCI Express 5.0/4.0/3.0/2.1/1.1 Core from Rambus
- PCIe 5.0 PHY in TSMC (16nm)
- Customizable Embedded Multi-port PCIe Switch
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- PCIe 5.0 Controller
- XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support