Physical Layer Back Plane Core
Features
- Operates in both 1394-1995 and 1394a back plane
- Implements 1394a Back plane PHY register set
- Single bit configures core for 1394-1995 operation or 1394a operation
- Supports 50 and 100 Mb/s transfer rates
- Performs clock recovery and synchronizes incoming data to local clock
- Performs system initialization and arbitration
- Separate transmitter and receiver
- Includes encode and decode functions for data strobe bit-level encoding
- Interoperates with Innovative?s line of application-specific Link Layer cores, and with commercially-available Link Layer Controller chips
- Available in synthesizable RTL
- Includes a comprehensive test bench and validation suite, synthesis scripts, and user documentation
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