The DP80390CPU is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. It supports up to 8 MB of linear code space and 16 MB of linear data space. This ratio is extended by an advanced power management PMU unit.
The DP80390CPU soft core is 100% binary-compatible with the industry standard 80390 & 8051 8-bit microcontroller. There are two configurations of DP80390CPU: Harvard, where internal data and program buses are separated, and von Neumann, with common program and external data bus. The DP80390CPU has a Pipelined RISC architecture and executes 85-200 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the 80C51 core, with the same settings. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion.
The DP80390CPU is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
Each of the DCD's 80390 Core has built-in support for the DCD Hardware Debug System, called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.
- software in 100% compatible with 80390 & 8051 industry standards
- LARGE mode - 8051 instruction set
- FLAT mode - 80390 instruction set
- Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
- Up to 14.632 VAX MIPS at 100 MHz
- 24 times faster multiplication
- 12 times faster division
- Up to 256 bytes of internal (on-chip) Data Memory
- Up to 8 MB of linear Program Memory
- 64 kB of internal (on-chip) Program Memory
- 8 MB external (off-chip) Program Memory
- Up to 16 MB of external (off-chip) Data Memory
- User programmable Program Memory Wait States
- User programmable External Data Memory Wait States
- De-multiplexed Address/Data bus, to allow easy memory connection
- Interface for additional Special Function Registers
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- 2 GHz virtual clock frequency in a 0.25u technological process
- pipelined RISC architecture
- more than 15. times faster than 80C51
- up to 14.632 VAX MIPS at 100 MHz