The XPS_GRAPHICS_ENGINE_V2_00_a IP core is 2D graphics rendering engine that interfaces to a PLB V4.6 bus for transfer of image data (master attachment) and for register access (slave attachment). The graphics engine uses a combination of dedicated graphics acceleration logic, a small footprint coprocessor and a PLB bus master attachment to render graphics. Using a command FIFO, commands containing instructions for rendering graphics primitives can be written by the host CPU, which will then be executed by the engine while the host CPU can continue with other tasks. Special hardware blocks accelerate plotting of single pixels as well as bit block transfers. The programmable coprocessor reads commands from the command FIFO and configures the dedicated hardware for drawing pixels and performing bit block transfers (bitblt). The coprocessor program is preloaded with the standard software, but it can be reloaded via the control registers. The IP core is intended for Xilinx based embedded FPGA designs.