English
180nm MTP Non Volatile Memory for Standard CMOS Logic Process
You are here:
PLB Bus SD Card Controller (SD/SDHC/MMC) with optional DMA engine
The XPS_SD_IF_V1_00_a IP core contains all the functions neede● d to interface a SD card to the PLB bus.
The core allows software to efficiently execute send commands and receive responses to/from the SD card command interface while at the same time performing data transfers over the 1 or 4 bit data interface.
Programming is simplified by the built-in command request/response state machine and command CRC generation/checking blocks built into the core. The optional DMA function allows the CPU to continue with other tasks while data is being transferred. To allow for an even smaller footprint core, the DMA function can be opted out leaving a FIFO interface instead.
The core allows software to efficiently execute send commands and receive responses to/from the SD card command interface while at the same time performing data transfers over the 1 or 4 bit data interface.
Programming is simplified by the built-in command request/response state machine and command CRC generation/checking blocks built into the core. The optional DMA function allows the CPU to continue with other tasks while data is being transferred. To allow for an even smaller footprint core, the DMA function can be opted out leaving a FIFO interface instead.
View PLB Bus SD Card Controller (SD/SDHC/MMC) with optional DMA engine full description to...
- see the entire PLB Bus SD Card Controller (SD/SDHC/MMC) with optional DMA engine datasheet
- get in contact with PLB Bus SD Card Controller (SD/SDHC/MMC) with optional DMA engine Supplier