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24-bit four channel audio ADC with 95 dB Dynamic Range, compatible with Automotive requirements
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PLB Bus SD Card Controller (SD/SDHC/MMC) with optional DMA engine
The XPS_SD_IF_V1_00_a IP core contains all the functions neede● d to interface a SD card to the PLB bus.
The core allows software to efficiently execute send commands and receive responses to/from the SD card command interface while at the same time performing data transfers over the 1 or 4 bit data interface.
Programming is simplified by the built-in command request/response state machine and command CRC generation/checking blocks built into the core. The optional DMA function allows the CPU to continue with other tasks while data is being transferred. To allow for an even smaller footprint core, the DMA function can be opted out leaving a FIFO interface instead.
The core allows software to efficiently execute send commands and receive responses to/from the SD card command interface while at the same time performing data transfers over the 1 or 4 bit data interface.
Programming is simplified by the built-in command request/response state machine and command CRC generation/checking blocks built into the core. The optional DMA function allows the CPU to continue with other tasks while data is being transferred. To allow for an even smaller footprint core, the DMA function can be opted out leaving a FIFO interface instead.
Features
- Compatible with SD Card Physical Layer System Specification 1.01
- Supports PLBv4.6 bus
- Optional PLB bus master DMA function for high speed transfer and CPU offloading
- Autonomous SD command execution with CRC generation and checking
- Data channel supports 1 or 4 bit interfaces and hardware CRC generation and checking
- Optional high performance DMA channel using PLB master port
- Programmable SD clock rates (up to 50 MHz)
- SD clock stopping for power reduction
- GPIO bits for card detection and write protection detection
- Supports SDHC cards
- MMC compatible
Benefits
- DMA is optional
Deliverables
- Netlist, datasheet, reference design
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