English
You are here:
PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process
Input 10M-200MHz, output 62.5M-1GHz, frequency synthesizable PLL, UMC 40 nm LP/RVT Low-K Logic process.
View PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process full description to...
- see the entire PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process datasheet
- get in contact with PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 62.5MHz - 1GHz, UMC 40nm LP process Supplier
PLL/DLL
- Programmable DLL, fully digital PLL - TSMC 28nm 28HP (CLN28HP)
- Programmable DLL, fully digital PLL - TSMC 40nm 40G (CLN40G)
- Programmable DLL, fully digital PLL - TSMC 40nm 40LP (CLN40lp)
- Second-Generation Digital Fractional-N PLL for Communications Applications
- Second-Generation Digital Fractional-N PLL for Logic Clocking
- Second-Generation Digital Fractional-N PLL for Low-Jitter Clocking