PLL (Frequency Synthesizer) IP, Input: 200MHz - 400MHz, Output: 200MHz - 400MHz, 400MHz - 800MHz, 800MHz - 1600MHz, UMC 55nm LP process
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz, frequency synthesizable PLL, ...
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