The VT18PLL500 is a macro cell for clock generation.
The output frequency is adjustable from 50 to 500MHz.
It is a fully integrated PLL based clock generator with a phase frequency detector (PFD), a low pass filter (LPF), a voltage controlled oscillator (VCO), and supporting circuitry such as fully programmable dividers. It is used for multiplication of stable clock source such as crystal oscillators.
Layout structure uses 1P4M (1poly and 4metal layers)
Layout does not use any special mask layer. (MIM or deep-Nwell layers are not required).
- 50 to 500Mhz output frequency
- 4 phases 0,90,180 &270 even in bypass mode
- 1P4M layout structure based on 0.18um 1P5M or 1P6M 1.8V logic process
- Single power supply 1.8V±10%, -40/+125°C
- Compact Die Size: [contact us]
- 50% duty cycle output.
- Low jitter
- Antenna diodes on each digital input.
- Design Kit includes:
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available
- Tapeout kit includes the design kit plus plysical view:
- LVS netlist and report
- DRC/ERC/ESD/ANT report