Phase-frequency detector (PFD) forms a control signal for VCO tuning. PFD compares phases of a divided VCO signal and a divided reference oscillator signal and detects phase difference. Charge pump (CP) generates pulses for the loop filter. The structure consists of two types of PFD with CP: ECL and CMOS choosing by a bit PFD_TP. The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with required value.
Reference frequency 24.84 MHz.
The block is fabricated on TSMC 0.18 um SiGe BiCMOS technology.
- TSMC BiCMOS SiGe 180 nm
- Input signals with low amplitude
- Low disbalance of output current
- High accuracy
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Phase-locked loop synthesizer