400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Polar Successive Cancellation (200 Gb/s) IP Core
Polar-SC-200G supports code block length (N) of 1024 and payload (K) of 854 bits with 20% coding overhead. It is customizable to other N and K on demand.
Polar-SC-200G employs fully-parallel and unrolled hardware architecture with
dedicated processing elements. It exploits pipeline depth optimization, register
balancing/retiming and adaptive quantization of LLR metrics.
The net coding gain of the selected (N=1024, K=854) polar code is 6.2 dB at 10^-12 BER.
Polar-SC-200G has been tested on Xilinx VCU128 Evaluation Kit with 16nm Virtex Ultrascale+ (xcvu37p-fsch2892-2L-e-es1) FPGA.
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