Power-on-Reset and Supply Monitoring - TSMC 40nm
Power-on Reset (POR) signal that monitors absolute value of three power supplies. POR signal includes programmable delay (during start-up only, brown-out has no assertion delay).
The POR includes internal Bandgap
Early Brown-out warning (EBW) signal that monitors absolute value of three power supplies.
Bypass Mode (BM) that enables complete override of POR signal putting the IP into low-power sleep mode,
Falling-edge-sensitive reset-signal impulse generator to notify external debug tools about reset condition from within the chip,
Test mode for easier on-chip debugging.
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Block Diagram of the Power-on-Reset and Supply Monitoring - TSMC 40nm

POR IP
- Power-On Reset (POR) - Flexible Threshold (down to 0.9V), Low Power (6µA) - XFAB 0.35 μm
- Advanced Power Controller w/ POR & BOR for PMU DC-DC and LDO ( Vin = 2.3-3.6V ) - TSMC 65nm
- Advanced Power Controller w/ POR & BOR for PMU DC-DC and LDO ( Vin = 1.5-1.9V ) - TSMC 28nm
- Advanced Power Controller w/ POR & BOR for PMU DC-DC and LDO ( Vin = 2.4-5V ) - SMIC 40nm
- Advanced Power Controller w/ POR & BOR for PMU DC-DC and LDO ( Vin = 2.4-3.6V ) - TSMC 55nm
- Advanced Power Controller w/ POR & BOR for PMU DC-DC and LDO ( Vin = 2.4-3.6V ) - SMIC 110nm