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Power-on-Reset and Supply Monitoring - TSMC 40nm
The S3PORT40LP is a low-power reset circuit that provides following features:
Power-on Reset (POR) signal that monitors absolute value of three power supplies. POR signal includes programmable delay (during start-up only, brown-out has no assertion delay).
The POR includes internal Bandgap
Early Brown-out warning (EBW) signal that monitors absolute value of three power supplies.
Bypass Mode (BM) that enables complete override of POR signal putting the IP into low-power sleep mode,
Falling-edge-sensitive reset-signal impulse generator to notify external debug tools about reset condition from within the chip,
Test mode for easier on-chip debugging.
Power-on Reset (POR) signal that monitors absolute value of three power supplies. POR signal includes programmable delay (during start-up only, brown-out has no assertion delay).
The POR includes internal Bandgap
Early Brown-out warning (EBW) signal that monitors absolute value of three power supplies.
Bypass Mode (BM) that enables complete override of POR signal putting the IP into low-power sleep mode,
Falling-edge-sensitive reset-signal impulse generator to notify external debug tools about reset condition from within the chip,
Test mode for easier on-chip debugging.
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Block Diagram of the Power-on-Reset and Supply Monitoring - TSMC 40nm
POR IP
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