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Power Architecture e200z1
Freescale’s e200 family of synthesizable, high-efficiency cores is intended for cost-sensitive, embedded real-time applications with significant performance requirements. The four e200 cores —e200z0, e200z1, e200z3, and e200z6—provide a range of features ideal for automotive, avionics, robotics, industrial control, medical devices, and compact networking applications.
Built to Power Instruction Set Architecture (ISA) Version 2.03, all four cores support variable length encoding (VLE); all except the z0 also implement the full 32-bit Book E instruction set. The cores offer low interrupt latency, AMBA AHB connectivity, and low-power design through clock gating. Debug features include static debug through Nexus Class 1 and real time debug through Nexus Class 2/3.
The small-footprint z0 core has a compact four-stage pipeline and runs only the VLE instruction set, which delivers exceptional code density. Reduced memory requirements and compact design make the z0 ideal for low-cost applications.
In addition to running the full 32-bit and VLE instruction sets, the z1 and z3 feature an MMU for full operating system support. For applications with significant signal processing requirements, the z3 also includes a signal processing engine (SPE) and single-precision floating-point unit (FPU), which often eliminates the need for an additional DSP.
The z6 is the highest-performance core of the family, with a seven-stage pipeline machine, all of the features of the z3, plus an integrated cache unit.
Built to Power Instruction Set Architecture (ISA) Version 2.03, all four cores support variable length encoding (VLE); all except the z0 also implement the full 32-bit Book E instruction set. The cores offer low interrupt latency, AMBA AHB connectivity, and low-power design through clock gating. Debug features include static debug through Nexus Class 1 and real time debug through Nexus Class 2/3.
The small-footprint z0 core has a compact four-stage pipeline and runs only the VLE instruction set, which delivers exceptional code density. Reduced memory requirements and compact design make the z0 ideal for low-cost applications.
In addition to running the full 32-bit and VLE instruction sets, the z1 and z3 feature an MMU for full operating system support. For applications with significant signal processing requirements, the z3 also includes a signal processing engine (SPE) and single-precision floating-point unit (FPU), which often eliminates the need for an additional DSP.
The z6 is the highest-performance core of the family, with a seven-stage pipeline machine, all of the features of the z3, plus an integrated cache unit.
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Block Diagram of the Power Architecture e200z1 IP Core
