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Power Architecture e200z6 (70038)
Freescale’s e200 family of synthesizable, high-efficiency cores is intended for cost-sensitive, embedded real-time applications with significant performance requirements. The four e200 cores available —e200z0, e200z1, e200z3, and e200z6—provide a range of features ideal for automotive, avionics, robotics, industrial control, medical devices, and compact networking applications.
Built to Power Instruction Set Architecture (ISA) Version 2.03, all four cores support variable length encoding (VLE); all except the z0 also implement the full 32-bit Book E instruction set. The cores offer low interrupt latency, AMBA AHB connectivity, and low-power design through clock gating. Debug features include static debug through Nexus Class 1 and real time debug through Nexus Class 2/3.
The small-footprint z0 core has a compact four-stage pipeline and runs only the VLE instruction set, which delivers exceptional code density. Reduced memory requirements and compact design make the z0 ideal for low-cost applications.
In addition to running the full 32-bit and VLE instruction sets, the z1 and z3 feature an MMU for full operating system support. For applications with significant signal processing requirements, the z3 also includes a signal processing engine (SPE) and single-precision floating-point unit (FPU), which often eliminates the need for an additional DSP.
The z6 is the highest-performance core of the family, with a seven-stage pipeline machine, all of the features of the z3, plus an integrated cache unit.
Built to Power Instruction Set Architecture (ISA) Version 2.03, all four cores support variable length encoding (VLE); all except the z0 also implement the full 32-bit Book E instruction set. The cores offer low interrupt latency, AMBA AHB connectivity, and low-power design through clock gating. Debug features include static debug through Nexus Class 1 and real time debug through Nexus Class 2/3.
The small-footprint z0 core has a compact four-stage pipeline and runs only the VLE instruction set, which delivers exceptional code density. Reduced memory requirements and compact design make the z0 ideal for low-cost applications.
In addition to running the full 32-bit and VLE instruction sets, the z1 and z3 feature an MMU for full operating system support. For applications with significant signal processing requirements, the z3 also includes a signal processing engine (SPE) and single-precision floating-point unit (FPU), which often eliminates the need for an additional DSP.
The z6 is the highest-performance core of the family, with a seven-stage pipeline machine, all of the features of the z3, plus an integrated cache unit.
Features
- Variable Length Encoding (VLE)
- VLE is a feature developed by Freescale and adopted by Power.org for inclusion in Power ISA Version 2.03. VLE optimizes code density by encoding 32-bit PowerPC instructions into mixed 16 and 32-bit instructions, reducing code footprint by up to 30 percent. 16 and 32-bit instructions may be freely intermixed. VLE is supported by most Power Architecture toolchains and is available on all four of the e200 family cores.
- Signal Processing Engine (SPE)
- SPE features available on the z3 and z6 cores provide single-instruction multiple-data (SIMD) operations—execution of one operation on multiple sets of data. On the z3 and z6 cores, SIMD support is coupled with a floating point unit (FPU) for enhanced DSP operation including 16 and 32-bit integer and fractional data types, signed and unsigned arithmetic, and IEEE single-length floating point operations, with double-precision support available through software.
- Memory Management Unit (MMU)
- The z1, z3, and z6 cores include an MMU, each with identical functionality and user interface, and cross-core code compatibility. The MMU is ideal for systems that require full operating system support. Its features include:
- Translation from 32-bit effective to 32-bit real addresses:
- 32-entry MMU in the z6
- 16-entry MMU in the z3
- 8-entry MMU in the z1
- Support for nine page sizes (4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, and 256 MB)
- Accesses qualified by:
- Address spaces: 2 data and 2 instruction
- 8-bit process identifier (supervisor accessible or global resource)
- Selectable access privileges:
- User Read/Write/Execute (UR/UW/UX)
- Supervisor Read/Write/Execute (SR/SW/SX)
- e200z6 CORE FEATURES:
- 7-stage pipeline with in-order execution
- Single-issue (one instruction issued per clock cycle)
- 32-bit Power Architecture Book E CPU core
- VLE for code density
- Unified 32-KB, 8-way set-associative cache
- 32-entry unified MMU
- SIMD and FPU for enhanced DSP support
- AMBA AHB 2.0 v6 bus interface
- Single-cycle execution for most instructions
- Integer and floating point multiply and multiply-accumulate in 3 clocks, fully pipelined
- Integer divide in 6 to 16 clocks, un-pipelined
- 3-cycle loads
- 1 to 3-cycle branches
- Small branch target address cache (BTAC) to accelerate loops
- Nexus Class 3 support
Deliverables
- Verilog source code
- Integration Testbench and Test-suite
- Comprehensive Documentation
- Scripts for simula
Block Diagram of the Power Architecture e200z6 (70038) IP Core
View Power Architecture e200z6 (70038) full description to...
- see the entire Power Architecture e200z6 (70038) datasheet
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