Power Management Unit (PMU) is designed to supply embedded integrated circuits with stable and precise internal voltage and currents. It integrates power switch element, LDO, Bangap and Power On Reset block.
PMU have controllable input voltage level and are complemented with VDD detectors to monitor the input voltage value. Two modes are available: full power mode and battery. If IO power voltage enable then LDO supply powered by 2.5V, if IO power voltage disable then LDO supply powered by battery power.
The voltage regulator consists of a differential amplifier which compares reference voltage with voltage from a feedback divider. It adjusts the impedance of a PMOS transistor for stabilization of output voltage at a set level.
PMU have Power On Reset block which generate logic level signal to control LDO power supply.
The block is fabricated on TSMC CMOS 65 nm technology.
- TSMC CMOS 65 nm
- Input voltage range from 0.9V to 2.8V
- Adjustable output voltage
- External output capacitor required
- Embedded power on reset module
- Low quiescent current
- Supported foundries: TSMC, UMC, Global Foundries
- Schematic or NetList
- Abstract view (.lef and .lib files)
- Layout (optional)
- Verilog behavior model
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Supply voltage sensitive circuits
- Battery-Powered equipment
- Power solutions