Power On Reset Circuit with RC-Oscillator in TSMC 40nm ULP

The S3PORT40LPD is a low-power reset circuit that provides
following features:
Power-on Reset (POR) signal that monitors absolute value of two power supplies. POR signal includes programmable delay (during start-up only).
The POR includes internal Bandgap Bypass Mode (BM) that enables complete override of POR signal putting the IP into low-power sleep mode,
Falling-edge-sensitive reset-signal impulse generator to notify e
xternal debug tools about reset condition from within the chip,
Test mode for easier on-chip debugging.

The S3PORT40LPD uses threshold-detect circuits to establish the
point when it is safe to operate internal circuits. This monitoring
ensures that all the power supplies reaches sufficient voltage levels
for correct operation. Next the POR goes into low power mode in
which it only operates to detect falling edges of the supplies.
The POR signal may be delayed where amount of the delay is
programmable via value of an external capacitor. The
S3PORT40LPD circuit is implemented in 40nm ultra lower-power
process (ULP). It is readily portable across all foundries and process
nodes upon request.

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