This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.18µm CL180G CMOS technology. The threshold sensing voltage can be configured from 1V to 1.3V (default is 1.15V). A hysteresis of 120mV is added to avoid false reset glitches in noisy supplies. This value can be digitally configured from 70mV to 200mV. The POR features an internal process compensated voltage reference. It requires an external 7.75nA current bias (sink), which can be implemented using chipus CM1014ff IP. The core is easily retargeted to any other CMOS technology.