The block consists of voltage detector, power on reset and NOR3 gate.
The voltage detector is a comparator that compares input voltage with reference voltages.
The power on reset is a special circuit that generates a signal after rising supply voltage required for the initial state of the triggers.
The block is designed on Global Foundries CMOS 55nm technology.
- Global Foundries CMOS 55nm
- Low current consumption
- Small area
- Supported foundries: TSMC, UMC, SMIC, iHP, AMS, Vanguard, SilTerra, X-FAB
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Power on reset
- Supply voltage level detector