This power switch has been designed for use with a load which consumes average current up to 77mA from the 1.8V Supply and 35mA from the 3.3V Supply.
The power switch contains two large PMOS transistors as the main switching devices, and an input buffer which provides non-overlapping signals to the switch.
As there is a capacitive loading from the digital logic, there is a resistor to slow down the rising edge of output voltage signal VDDO. A switch-on that is too fast would cause a current peak, which could affect other circuits.
The Power switch has been implemented in a standard 6 metal 28nm basic logic process with no analog options. It is readily portable to any similar manufacturing process, and any activity of this nature is fully supported.
- 28nm SLP Process, with Deep-Nwell option
- 1.8V I/O and standard logic devices
- 3.3V, 1.8V and 1.0V Supply
- Voltage drop:
- TBDmV: ILOAD = 77 mA from 1.8V Supply
- TBDmV: ILOAD = 35 mA from 3.3V Supply
- Single 1.0 V control input
- Power Down Control
- Low Leakage: TBD nA
- Compact Die Area: 0.1 mm2
- Operating from 1.8V, 3.3V and 1.0V supply the S3PMGF28SLP dissipates only TBD uW under nominal operating conditions and has an extremely small die area of only 0.1mm2.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (.lib)
- Behavioral Model (Verilog)
- Integration Support
Block Diagram of the Power Switch Circuit IP Core