130nm OTP Non Volatile Memory for Standard CMOS Logic Process
Powerline (PLC), Wireline, G.hn, G,Fast, Analog Front-End (AFE) ultra-efficient Area and Power
The AFE incorporates on the transmit side the TX DAC to the current amplifier (IAMP), whilst on the receive side, it includes the analog channel equalizer (ACE) to the PGA and ADC.
The clock reference circuitry consists of a PLL, Clock Buffers and Clock routing.
The TX-Path DAC is a 12-Bit Current DAC (TX-DAC). The TX-DAC is followed by a Current Amplifying Block (TX IAMP) with a gain range of 24dB in 1dB steps. The TX IAMP interfaces to the line, supporting a transmit power of 4dBm into 100 Ohms termination on the line through the line interface
The RX Path consists of an RX PGA that interfaces to the line and has a gain range of -15dB to +24dB in 1dB Steps. The RX PGA is followed by a 424MSPS 12Bit SAR-ADC (RX-ADC) which passes the converted data to the Digital Modem.
The Support Blocks of the AMB include I/O Cells, reference oscillator, PLL, clock distribution tree, voltage and current references, LDO’s and control circuitry.
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