PowerMiser(TM) delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques eliminate performance compromises that impact active power at lower operating voltages. Retentive sleep modes, including light sleep for rapid wake-up, and deep-sleep for maximal leakage current savings, are provided. sureCore compilers support capacities up to 576Kbit with word lengths up to 144bits with three multiplexing factors; 4, 8 and 16. The compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.
- Up to 60% dynamic power savings
- Up to 25% static power savings
- Delivers both dynamic power savings and static power savings compared to industry standard SRAMs
- Ideal for replacing current SRAM IP and delivering SoC-wide power benefits