Core1588 provides hardware support for the implementation of an IEEE 1588 Precision Time Protocol (PTP) capable system. A firmware component that interacts with Core1588 will also form part of such a system. Core1588 maintains a real-time counter (RTC) and monitors the Ethernet MAC-PHY interface to identify IEEE 1588 type frames. The core timestamps receipt and transmission of these frames and, when enabled, can interrupt the system processor to cause action to be taken. Core1588 supports full duplex operation. An APB interface is present on the core and this allows the system processor to control how the core operates and to retrieve timestamp information. Complete block diagram and core description can be found in the Core1588 Handbook.
Key features of Core1558:
* Real-time clock (RTC) (32-bit seconds counter and 32-bit nanoseconds counter)
* Supports up to 3 latch inputs and up to 3 trigger outputs
* APB interface for processor access
* RTC value can be written directly
* RTC can be speeded up or slowed down
* Monitors RMII interface to detect IEEE 1588 frames
* Supports full duplex operation
* Can generate interrupt when IEEE 1588 frame detected or when latch/trigger event occurs
* Supports 100 Mbps operation only
The IEEE 1588 Precision Time Protocol (PTP) allows synchronization of devices connected to an Ethernet network with a high level of accuracy. One of the devices on the network serves as the master clock. The other devices behave as slave clocks synchronizing to the master clock's value. The master clock is dynamically selected among the PTP capable devices on the network. The IEEE 1588 best master clock (BMC) algorithm is used to determine which device should be used as the master clock device. This algorithm uses the clocks characteristics broadcast on the network through announce messages to determine which clock is the most accurate. Once the BMC algorithm has completed, the master clock starts sending synchronization messages at regular intervals. Slave clocks use these synchronization messages along with communication path delays measurements to adjust their local clock to synchronize with the master clock.
The SmartFusion™ IEEE 1588 Reference Design demonstrates the use of Core1588 IP on a SmartFusion device as part of an IEEE 1588 over Ethernet boundary clock implementation. This reference design is targeted at the SmartFusion Evaluation Board. The SmartFusion IEEE 1588 Reference Design demonstrates the following Core1588 IP features:
* IEEE 1588 Ethernet packets timestamping
* Synchronization of the precision time clock with a master clock
* Latching of the master synchronized time on input latch assertion
* Triggering output pulses when the synchronized clock reaches specified values
The reference design includes a web server, allowing observation of the current state of the PTP clock, and exercises the Core1588 input latches and output triggers.