An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS designs. The process detector provides the means to assess process variation from die to die and on chip variation across large die. Process detectors are especially useful in the bring up and characterization phase of new silicon, assessing and compensating for ageing and minimizing voltage guard bands through voltage scaling schemes. This In-Chip Sensing and PVT Monitoring IP is available as part of the Synopsys DesignWare® Foundation IP portfolio. It also forms the foundation of the new Synopsys Silicon Lifecycle Management (SLM) platform. SLM enables new levels of insight for both SoC providers as well as their customers to optimize operational activities at each stage of the device and system lifecycles from design to in-field.