Processor Core
The MD5 algorithm is an improved version of the MD4, created by Professor Ronald L. Rivest of MIT, and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 128-bit (4 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message.
The MD5 core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs.
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Block Diagram of the Processor Core IP Core

Processor Core IP
- RT-660-FPGA DPA-Resistant Programmable Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140
- RT-630-FPGA Programmable Root-of-Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- RT-640 Programmable Root-of-Trust Security Processor for Automotive ASIL-B-ready
- RT-645 Programmable Root-of-Trust Security Processor for Automotive ASIL-D-ready
- Deep Learning Processor
- Near-threshold voltage and ultra-wide dynamic voltage and frequency scaling (UW-DVFS)