The programmable CMOS frequency divider is a set of 8 serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The dividing ratio is 2…511.
Input frequency is 88...500 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
- iHP SGB25V
- Range of dividing ratio 2…511
- Maximum input frequency 500 MHz
- Compact structure
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- PLL frequency synthesizer