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Programmable 9-bit CMOS low-frequency divider (5...511 dividing ratio)
The programmable CMOS low-frequency divider design is based on the 9-bit counter. Since this structure consists of the static triggers, current consumption is closed to zero when there is no input clock. The dividing ratio is 5...511.
Input frequency is 26...300 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Input frequency is 26...300 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Features
- iHP SGB25V
- Dividing ratio: 5…511
- Compact structure
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Applications
- PLL frequency synthesizer
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