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Low latency Network TAP IP-Core for full duplex 100M/1G Ethernet links
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Programmable CMOS frequency divider (32...16383 dividing ratio)
The programmable CMOS frequency divider is a set of serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The dividing ratio is 32...16383.
Input frequency is 100...1050 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Input frequency is 100...1050 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Features
- iHP SGB25V
- Wide range of dividing ratio (32-16383)
- Low current consumption
- Compact structure
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Applications
- PLL frequency synthesizer
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