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Programmable CMOS frequency divider (56..16383 dividing ratio)
The cell is 14-bit programmable frequency divider. It consists of CMOS prescaler with variable dividing ratio 8/9 controlled by 3-bit swallow counter and CMOS 11-bit counter. The dividing ratio is 56…16383 and current consumption weakly depends on operating frequency (50..1050 MHz).
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Features
- iHP SGB25V
- Programmable dividing ratio (56..16383)
- Wide frequency range (50..1050 MHz)
- Small area
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Applications
- PLL frequency synthesizer
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