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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Programmable CMOS HF divider (16…4095 dividing ratio)
The programmable CMOS frequency divider consists of two independent circuits. The first one a set of 8 serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The second divider is based on the prescaler with the varied dividing ratio 4/5 and the two programmable binary-decimal counters.
The dividing ratio is 16…4095. Input frequency is 1000...1900 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
The dividing ratio is 16…4095. Input frequency is 1000...1900 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
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