The divider consists of the input signal preamplifier (buffer), the converter of a differential input signal to an unipolar signal with a supply voltage peak-to-peak, the prescaler with variable dividing ratio 4/5 and the programmable divider on the basis on two binary decade counters.
The block is fabricated on TSMC BiCMOS 0.18 um.
- TSMC BiCMOS 0.18 um
- Wide range of dividing ratio (21…4097)
- Low current consumption 2.1 mA
- Compact structure
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- PLL frequency synthesizer