The cell is 14-bit programmable frequency divider. It consists of ECL prescaler with variable dividing ratio 8/9 controlled by 3-bit swallow counter and CMOS 11-bit counter. The dividing ratio is 56…16383 and current consumption weakly depends on operating frequency (50..1050 MHz).
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
- HP SGB25V
- Programmable dividing ratio (56 to 16383)
- Wide frequency range (50 to 1050 MHz)
- Small area
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- PLL frequency synthesizercy synthesizer