PUFrt-based secure storage supports XIP
With real-time encryption/decryption based on the unique randomness built into each on-board PUF, PUFflash supports execution in place (XIP) while offering secure data-at-rest protection for sensitive code and data.
An optional error correction code (ECC) can be implemented with the embedded Flash as well, further guaranteeing data stability over the lifetime of the system.
A standard APB slave control module allows for easy drop-in integration of PUFflash for systems that already support ARM’s peripheral bus protocol. By unifying both PUFrt and Flash under the APB, system integrators can work with a familiar interface to execute the various RoT and embedded Flash functions of PUFflash.
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Block Diagram of the PUFrt-based secure storage supports XIP IP Core

Flash Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- xSPI Flash Memory Controller
- Hyperbus Flash Memory Controller
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- SPI Flash Memory Controller
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