The Xilinx® LogiCORE™ QDMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block. The IP provides an optional AXI4-MM or AXI4-Stream user interface.
The QDMA solution provides support for multiple Physical/ Virtual Functions with scalable queues, and is ideal for applications that require small packet performance at low latency.
The QDMA solution is available for early access beta customers in 2018.1 (April, 2018).
- Supports 64, 128, 256 and 512-bit data path
- Supports x1, x2, x4, x8, or x16 link widths.
- Supports Gen1, Gen2, and Gen3 link speeds
- Support for both the AXI4-Memory Mapped and AXI4-Stream interfaces per queue
- 2K queue sets
- 2K H2C Descriptor rings
- 2K C2H Descriptor rings
- 2K C2H Write back rings
- Supports Polling Mode (Status Descriptor Write Back)
- C2H Stream interrupt moderation
- C2H stream CMPT entry coalesce
- Descriptor and DMA Customization through user logic
- Allow Custom Descriptor format
- Traffic Management
- Supports SR-IOV up to 4 Physical Functions and 252 Virtual Functions
- Thin Hypervisor model
- Allows only privileged/Physical function (PF) to program contexts and registers
- Function Level Reset support
- 2K MSI-X vectors
- Up to 8 MSI-X per function
- Interrupt coalescing