The Xilinx Ethernet Quad Serial Gigabit Media Independent Interface PCS/PMA or QSGMII IP LogiCORE™ IP provides an Ethernet Physical Coding Sublayer (PCS) with an aggregation of four 10/100/1000M ports to one five gigabit transceiver. QSGMII interfaces are implemented using transceivers in Virtex®-7 or Kintex™-7 devices. On the front end, the LogiCORE IP can also interface seamlessly to four Ethernet MACs through a built-in Gigabit Media Independent Interface (GMII). This IP is available through CORE Generator™ software at no charge to help you accelerate your time to market. It is built upon our existing Serial Gigabit Media Independent Interface PCS/PMA IP.
- Designed to Cisco’s proprietary QSGMII specification version 1.2
- Implements 4 lanes of 10/100/1000 Mbps channels
- IEEE 802.3-2008 Clause 36 implementation of PCS (Physical Coding Sublayer) for encapsulation, line encoding and link synchronization
- Available at no charge in CORE Generator
- Supports internal or external GMII for interfacing to a MAC or customer logic
- Integrated with the Xilinx 7-series embedded transceivers
- Available in VHDL or Verilog netlist simulation model