The QSPI-XIP core implements a quad Serial Peripheral Interface (SPI) module that either controls a serial data link as a master, or reacts to a serial data link as a slave.
Users can configure the core via software control to be a master or slave device. Reading and writing the core is done on the AMBA® AHB or AXI bus interface. The core operates in various data modes from 4 to 32 bits (eight modes are supported in multiples of four data bits). The data is then serialized and transmitted, either LSB or MSB first, using the standard four-wire SPI bus interface or the extended Dual or Quad Bus modes.
The QSPI-XIP core is compatible with various industry-standard DMA controllers. Enabling DMA operation assists a DMA controller in the loading (writing) of the transmit FIFO, and the unloading (reading) of the receive FIFO.
The Execute in Place (XIP) Mode allows an AHB or AXI Master to directly read the contents of any of several industry-standard flash devices (such as Winbond, Macronix, Spansion, and Micron devices) simply by reading from the address space of the QSPI Controller.
The QSPI-XIP core can be used with up to four SPI slave devices.
- Compatible with many industry-standard serial Flash devices
- Execute in Place (XIP) mode
- AMBA® AHB or AXI4 interface
- DMA Interface
- Master or Slave mode
- Single, Dual and Quad-bit modes
- 4-bit to 32-bit serial TX/RX
- Full duplex operation
- Half-duplex operation support
- Separate SCLK input for Master Mode
- 8 to 256 word TX/RX FIFO, configurable
- Asynchronous Slave Interface
- Interrupt control
- LSB or MSB mode
- Up to four slaves under Master control
- Motorola Serial Peripheral Inter-face (SPI) format support
- TI Synchronous Serial Frame format support
- National Microwire Frame format support
- XIP feature can optionally be removed
- Verilog source or FPGA netlist
- Testbench and vectors
- Sample synthesis and simulation scripts
- AXI Bus Functional Model
- C-Sample Code
- User Documentation
Block Diagram of the QSPI Controller with XIP IP Core