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QSPI FLASH Controller with Execute in place – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
The DFSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. The DFSPI controller is fully compatible with the HyperBusTM specification, xSPI (Expanded Serial Peripheral Interface – JESD251A) specification and XccelaTM Bus Interface. The SPI Controller allows easy communication with most available SPI FLASH memories.
A serial clock line (SCK) synchronizes shifting and sampling of the information on the serial data lines. It is a technology independent design that can be implemented in a variety of process technologies. The DFSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.
The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, which means it is delivered in the exact configuration that meets users’ requirements.
A serial clock line (SCK) synchronizes shifting and sampling of the information on the serial data lines. It is a technology independent design that can be implemented in a variety of process technologies. The DFSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.
The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, which means it is delivered in the exact configuration that meets users’ requirements.
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