The Controller and PHY IP for Quad Serial-Peripheral Interface (QSPI) - efficient, silicon proven and fully customizable design. The Controller enables access to Serial Flash devices, while providing various modes of operation and improved high speed read data capture mechanism. It also includes an integrated soft PHY to improve timing for higher speed QSPI interfaces.
For indirect operations, data is transferred between system memory and external Flash memory via an internal SRAM which is loaded for writes and unloaded for reads by an AHB master within the system-on-chip (SoC) environment at low latency AHB system speeds.
The QSPI Controller and PHY IP provides higher performance, smaller form factor and lower power for consumer, enterprise, mobile, automotive and IoT products. With today high adoption of Flash memory in wide variety of products and segments it is necessary to choose the right product for a complicated design. The Cadence controller and PHY IP for QSPI guarantees quality and easy adoption.