TRC3104SBA is a Quad SerDes transceiver device, capable of transmitting 1.06 to 3.125Gb/s signals over Backplane, Fiber Channel, and cupper cables. It uses single and double data rate capability. One 1.8V supply can power the core and I/Os. It has Comma detector, low jitter clock synthesizer, 8B/10B converter, selectable pre-emphasis and equalizer, CDR PLL, BIST and loopback functions for testing, and needs only 3 external resistors for setting bias current. It is also available as core (named TRC3104CBA).
- Quad channel optimized for backplane , but can be used for FC and cable applications as well.
- Data rate 1 to 3.125Gb/s on high speed differential lines.
- Jitter tolerance of 0.72UIpp, and Jitter generation of 0.19UIpp.
- On chip 8bit/10bit encoder/decoder.
- selectable equalizer and pre-emphasis.
- Loopback abd BIST function (PRBS7 pattern).
- On chip JTAG and MDIO for test and setup.
- 256 pin PBGA package with 400mW per channel Pd.
- TRC3104SBA stand alone chip.
- TRC3104CBA core.
Block Diagram of the Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes IP Core